Apple’s M‑series processors have historically followed a monolithic design philosophy. Each generation from M1 through M4 relied on a single die that integrated CPU cores, GPU cores, memory controllers, and specialized accelerators into a unified system on chip. With the introduction of the M5 Pro and M5 Max processors, Apple has fundamentally altered this approach.

The company has introduced a modular design methodology now, in 2026, known as Fusion Architecture.

Fusion Architecture represents the first structural redesign of Apple Silicon since the debut of the M1 in 2020. Instead of manufacturing one large die, Apple now constructs high‑end processors from multiple silicon dies bonded together into a single logical system. This shift reflects broader trends in semiconductor engineering driven by manufacturing limits, cost constraints, and the rapidly growing computational requirements of artificial intelligence workloads.

When Apple introduced the M1 processor in 2020, the company redefined personal computing processor architecture. The M1 integrated CPU, GPU, Neural Engine, and memory controllers onto a single die while introducing the unified memory architecture. This architecture allowed all compute components to access a shared memory pool without copying data between discrete subsystems.

This design delivered several advantages including reduced memory latency, improved energy efficiency, higher effective bandwidth between compute units, and simplified software optimization. The M1 architecture quickly proved successful and subsequent generations including M2, M3, and M4 followed the same structural model while incrementally improving process nodes, core counts, and bandwidth.

However, this design philosophy carried a significant limitation. As workloads increased, particularly those related to large language models and machine learning inference, chip complexity and die size began to scale rapidly. Larger dies are significantly harder to manufacture reliably because even a single defect renders the entire chip unusable.

Apple is not alone in confronting the physical limits of monolithic chips. The semiconductor industry has broadly transitioned toward chiplet architectures where processors are composed of several smaller dies interconnected within a single package.

Major vendors have already adopted this strategy. AMD employs chiplet designs in Ryzen and EPYC processors. Intel uses advanced packaging techniques such as embedded multi‑die interconnect bridge and Foveros stacking. NVIDIA constructs its largest AI accelerators using multi‑die packaging.

The economic rationale behind chiplets is straightforward. Manufacturing several smaller dies is more cost efficient than producing one extremely large die because yield rates improve significantly. Industry analyses indicate that modular chiplet designs can deliver comparable computational capability at dramatically lower manufacturing cost.

This transition marks the gradual decline of the traditional monolithic processor model.

Apple’s response to these constraints is Fusion Architecture.

Rather than simply replicating existing dies and connecting them together, Apple has designed a modular structure where individual dies perform distinct functional roles. These dies are physically bonded using high bandwidth interconnect technology and presented to the operating system as a single logical processor.

The critical design requirement Apple preserved is unified memory. Even though the processor now spans multiple dies, Apple maintains a shared memory architecture that allows all compute units to operate on the same dataset without explicit data transfers.

While Apple has not publicly disclosed the full technical implementation of cross die memory coherence, the company claims the architecture preserves the same software model as earlier M series chips. From the perspective of applications and operating systems, the processor behaves as a single unified system.

The first processors implementing Fusion Architecture are the M5 Pro and M5 Max. Both chips consist of two separate dies connected through high speed packaging technology. The first die is identical in both processors and contains the majority of the system control components.

The first die includes an 18 core CPU cluster, a 16 core Neural Engine, the SSD controller, and Thunderbolt I O controllers. This die effectively functions as the computational and system management foundation of the processor.

The second die differentiates the two processors.

The M5 Pro configuration includes up to 20 GPU cores, a single media engine, and a memory controller delivering up to 307 GB per second bandwidth. The M5 Max configuration includes up to 40 GPU cores, dual media engines, and a memory controller delivering up to 614 GB per second bandwidth.

This design enables Apple to scale GPU and media performance independently from the CPU subsystem. In principle, additional GPU focused dies could be added in future designs to extend compute capacity without redesigning the entire processor.

The CPU configuration of the M5 generation introduces another major structural change. Earlier M series chips relied on a hybrid architecture combining performance cores with efficiency cores.

The M5 Pro and M5 Max abandon efficiency cores entirely and instead implement a two tier high performance structure.

The CPU cluster consists of six super cores optimized for peak single thread performance and twelve performance cores optimized for high multithread throughput. This creates an all performance architecture designed for sustained computational workloads rather than energy optimized background processing.

The naming scheme has also evolved. What were previously called performance cores in earlier M series chips are now referred to as super cores. The new performance cores represent an intermediate tier that prioritizes throughput while maintaining strong efficiency characteristics.

This structure closely resembles the strategy used by AMD in its Zen 5 and Zen 5c core architecture.

Another significant development is the integration of neural accelerators within each GPU core.

Although the GPU core counts remain unchanged from the previous generation, each core now includes dedicated hardware for machine learning computation. This allows the GPU to perform both graphics processing and AI inference tasks.

Apple claims this architecture enables up to four times the AI compute capability without increasing the overall GPU core count.

This reflects a broader shift in processor design. GPUs are evolving into general purpose parallel compute engines where graphics workloads represent only one category of computation.

Large AI models require extremely high memory bandwidth to deliver acceptable inference performance. Apple has continued to increase bandwidth across successive M series generations. The M5 generation extends this trend. The M5 Pro reaches 307 GB per second memory bandwidth while the M5 Max reaches 614 GB per second. Both figures represent improvements over the M4 generation.

Bandwidth scaling is particularly important for local inference of large language models. High bandwidth allows large parameter sets to be accessed efficiently by GPU and neural compute units. This suggests Apple is designing these processors with the expectation that laptops will increasingly run advanced AI models locally rather than relying solely on cloud infrastructure.

Fusion Architecture is not revolutionary in the sense that multi die packaging already exists across the semiconductor industry. However, it represents a critical strategic transition for Apple Silicon. The key significance lies in scalability. By demonstrating that unified memory and high performance interconnects can function across multiple dies, Apple removes the traditional constraint of die size. Future processors can scale horizontally by combining additional specialized dies rather than enlarging a single monolithic chip.

This opens several potential directions for future development including additional GPU dies for AI acceleration, specialized machine learning dies, and advanced multi package configurations for workstation and server workloads. The packaging technology used to bond these dies is similar to the interconnect technologies used in modern AI servers. Apple has effectively brought data center class packaging techniques into consumer laptop processors.

The M1 generation introduced a radical rethinking of personal computing processors through unified memory and system level integration. Subsequent generations refined that architecture while maintaining the monolithic design.

Fusion Architecture represents the next phase of Apple Silicon (r)evolution. Author notes the reader to remember 2020 and how revolutionary the M1 Apple Silicon architecture actually was.

Instead of competing with the physical limits of monolithic chips, Apple is adopting a modular strategy that preserves its core architectural principles while enabling future scalability. Multi die packaging allows the company to expand computational capability without incurring the manufacturing penalties associated with extremely large silicon dies.

The immediate performance gains of the M5 generation are important but the more significant development is architectural. Fusion Architecture establishes the structural foundation upon which future Apple processors will be built.

In practical terms, the question is no longer how large a single Apple Silicon chip can become. The real question is how many modular components Apple can connect together while maintaining the unified architecture that has defined the platform since the M1.

Terence Tao is another remarkable figure who deserves a Nobel Prize. However, since there isn't a Nobel Prize for mathematics, the highest honor he can receive is the Fields Medal, which he has already won.

Amadeus #Mozart, go Bob Dylan!

Having dropped all my current articles, this post is intended to sum it all up.

XML and XML Schema territory:

• Type Systems Compared - XML <> CLR (XML, XML Schema, CLR) [Preview, Download]
• The Importance of XML Typization (XML, XML Schema) [Preview, Download]
• XML Namespaces and PSVI Problems (XML, XML Schema) [Preview, Download]
• XML Schema - Specification Primer (I/II) (XML, XML Schema) [Preview, Download]
• XML Schema - Specification Primer (II/II) (XML, XML Schema) [Preview, Download]

WinFX territory:

• Concepts and Semantics of Service Contracts (WCF) [Preview, Download]
• Transactional Semantics in Loosely Coupled Distributed Systems (WCF) [Preview, Download]
• Cooperation Between Workflows and Services (WCF, ASMX, WF) [Preview, Download]

Article language: Slovenian

Last article discusses service-workflow cooperation options in WinFX and dives into communication scenarios for Windows Workflow Foundation.

Language: Slovenian

Naslov:

Sodelovanje storitev in delovnih tokov

Last article finished my XML series. This one focuses on transactional semantics in a service oriented universe.

Language: Slovenian

Naslov:

Transakcijska semantika v šibko sklopljenih, porazdeljenih sistemih

Next article in XML series is discussing XML Schema. This is a two part article.

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Naslov:

XML Schema (1/2)

XML Schema (2/2)

Next article in XML series is discussing XML Namespaces and PSVI problems.

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Naslov:

Imenski prostori XML in problemi v PSVI

This article is starting the XML series. First we dive into XML typization importance and XML Infoset.

Language: Slovenian

Naslov:

Pomembnost tipizacije XML

The second article is about concepts and semantics of service contracts. It deals with WCF (Windows Communication Foundation) contract definition and its behavioral aspects.

Language: Slovenian

Naslov:

Koncepti in semantike storitvenih pogodb